Cypress Semiconductor /psoc63 /USBFS0 /USBHOST /HOST_EP2_CTL

This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40.

• If automatic buffer transfer mode (DMEA=‘1’) is used, this Endpoint must not set from 0 to 2.

When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. ‘0’ : Releases the NULL automatic transfer mode. ‘1’ : Sets the NULL automatic transfer mode. Note :

• For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.

This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. ‘0’ : Releases the automatic buffer transfer mode. ‘1’ : Sets the automatic buffer transfer mode. Note :

• The CPU must not access the send/receive buffer while the DMAE bit is set to ‘1’. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).

This bit specifies the transfer direction the Endpoint support. ‘0’ : IN Endpoint. ‘1’ : OUT Endpoint Note:

• This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is ‘1’.

This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to ‘0’ before clearing the BFINI bit. ‘0’ : Clears the initialization. ‘1’ : Initializes the send/receive buffer Note :

• The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits.